The present invention generally relates to interconnection structures for joining an integrated semiconductor device or xe2x80x9cchipxe2x80x9d to a carrier substrate of organic nature. More particularly, the present invention concerns an interconnection structure separable into a plurality of individual chip modules, and a method of making the interconnection structure and a high volume of the individual modules. The present invention is especially concerned with xe2x80x9ccontrolled collapse chip connectionxe2x80x9d or xe2x80x9cC4xe2x80x9d structures that employ solder-bump interconnections, which is also referred to as xe2x80x9cface downxe2x80x9d or xe2x80x9cflip-chipxe2x80x9d bonding.
Controlled collapse chip connection (C4) or flip-chip technology has been successfully used for over twenty-five years for interconnecting high I/O (input/output) count and area array solder bumps on silicon chips mounted to base ceramic chip carriers, for example alumina carriers. The solder bump, typically a 95 Pb/5 Sn alloy, provides the means of chip attachment to the ceramic chip carrier for subsequent usage and testing. For example, see U.S. Pat. Nos. 3,401,126 and 3,429,040 to Miller and assigned to the assignee of the present disclosure, for a further discussion of the controlled collapse chip connection (C4) technique of face down bonding of semiconductor ships to a carrier. Typically, a malleable pad of metallic solder is formed on the semiconductor device contact site and solder joinable sites are formed on the chip carrier.
The solder joinable sites on the carrier are surrounded by non-solderable barriers so that when the solder on the semiconductor device contact sites melts, surface tension of the molten solder prevents collapse of the joints and thus holds the semiconductor device (chip) suspended above the carrier. With the development of the integrated circuit semiconductor device technology, the size of individual active and passive elements have become very small, and the number of elements in the device has increased dramatically. This results in significantly larger chip sizes with larger numbers of I/O terminals. This trend will continue and will place increasingly higher demands on device forming technology. An advantage of solder joining a device to a substrate is that the I/O terminals can be distributed over substantially the entire surface of the semiconductor device. This allows efficient use of the entire surface, which is more commonly known as area bonding.
Usually the integrated circuit semiconductor chips are mounted on supporting substrates made of materials with coefficients of expansion that differ from the coefficient of expansion of the material of the semiconductor chip, e.g., silicon. Normally, the chip is formed of monocytstalline silicon with a coefficient of expansion of 2.6xc3x9710xe2x88x926 per xc2x0 C. and the substrate is formed of a ceramic material, typically alumina with a coefficient of expansion of 6.8xc3x9710xe2x88x926 per xc2x0 C. In operation, the active and passive elements of the integrated semiconductor chip inevitably generate heat resulting in temperature fluctuations in both the chips and the supporting substrate since the heat is conducted through the solder bonds. The chips and the substrate thus expand and contract in different amounts with temperature fluctuations, due to the different coefficients of expansion. This imposes stresses on the relatively rigid solder terminals.
The stress on the solder bonds during operation is directly proportional to (1) the magnitude of the temperature fluctuations, (2) the distance of an individual bond from the neutral or central point (DNP), and (3) the difference in the coefficients of expansion of the material of the semiconductor device and the substrate, and is inversely proportional to the height of the solder bond, that is the spacing between the device and the supporting substrate. The seriousness of the situation is further compounded by the fact that as the solder terminals become smaller in diameter in order to accommodate the need for greater density, the overall height decreases.
The disclosure of an improved solder interconnection structure with increased fatigue life can be found in U.S. Pat. No. 4,604,644 to Beckham et al., and assigned to the assignee of the present disclosure, the entire contents of which are incorporated herein by reference. In particular, U.S. Pat. No. 4,604,644 discloses a structure for electrically joining a semiconductor device to a support substrate that has a plurality of solder connections where each solder connection is joined to a solder wettable pad on the support substrate. A dielectric organic material is disposed between the peripheral area of the device and the facing area of the substrate, and this material surrounds and encapsulates at least one outer row and column of solder connections but leaves the solder connections in the central area of the device free of the dielectric organic material. The dielectric material is typically applied by first mixing it with a suitable solvent and then dispensing it along the periphery of the device where it can be drawn in between the device and substrate by capillary action.
Encapsulants that exhibit, among other things, improved fatigue life of C4 solder connections are disclosed in U.S. Pat. No. 4,999,699 to Christie et al. and assigned to the assignee of the present disclosure, the entire contents of which are incorporated herein by reference. In particular, U.S. Pat. No. 4,999,699 discloses a curable composition containing a binder which is a cycloaliphatic polyepoxide and/or a cyanate ester or prepolymer thereof and a filler. U.S. Pat. No. 5,121,190 to Hsiao et al. and assigned to the assignee of the present disclosure, the entire contents of which are incorporated herein by reference, discloses providing C4 solder connections for an integrated semiconductor device on an organic substrate. The compositions disclosed therein are curable compositions containing a thermosetting binding and filler. The binder employed has viscosity at normal room temperatures (25xc2x0 C.) of no greater than about 1,000 centipoise. Suitable binders disclosed therein include polyepoxides, cyanate esters and prepolymers thereof.
In addition, U.S. Pat. No. 5,536,765 to Papathomas and assigned to the assignee of the present disclosure, the entire contents of which are incorporated herein by reference, discloses compositions that exhibit excellent wetting and coverage of the C4 connections as well as the pin heads under the device that are present. In fact, these compositions make it possible to achieve complete coverage beneath the chip. These compositions, which include a triazine polymer that is a reaction product of (a) monocyanate and (b) dicyanate and/or a prepolymer thereof, are of relatively low viscosity prior to curing and thereby exhibit even and adequate flow under the semiconductor device. The solder interconnection for forming connections between an integrated semiconductor device and a carrier substrate includes a plurality of solder connections that extend from the carrier substrate to electrodes on the semiconductor device to form a gap between the carrier substrate and the semiconductor device. The gap is filled with a composition obtained from curing the disclosed composition.
The techniques described above enable chips to be attached directly on the surface of a board thereby eliminating an intermediate chip carrier. Although these techniques have been quite successful, there still remains room for improvement, especially with respect to the handling and rate of producing modules with organic base panels, such as those made of Teflon. Organic based modules are very prone to handling damage when assembled individually in accordance with past practices. Individual assembly is also costly per module because of the amount of handling and manipulation required to assemble each small module element one at a time, resulting in low yields of the assembled modules.
The present invention overcomes the foregoing problems of the prior art in that it provides a method and structure for producing a plurality, e.g., 80 to 100, individual organic based modules from a single composite panel formed as a laminate of relatively large individual panel elements. The composite panel contains a plurality of compartments each housing one or more chips, and this composite panel is then cut into individual modules each having one or more compartments. The present disclosure thereby provides a method and structure for producing individual chip modules in high yields at relatively low costs per module. Damage to the modules produced is also greatly reduced because handling and manipulation of the small module elements and of the assembled modules are minimized.
The advantageous method of the invention includes the following steps. An organic base panel, such as one made of Teflon and having small terminal pads with solder stubs on its upper side, is placed on a carrier plate having three locator pins. A metal stiffener panel is placed on the upper side of the organic base panel with a silicone based adhesive therebetween. The stiffener panel is preferably made of metal and has a plurality of openings to define compartments for later housing one or more chips. A clamping plate is then fastened to the carrier plate to keep the two module panels flat and to squeeze the silicone adhesive to the proper thickness as it is cured by placing the clamped structure in an oven. The two module panels and the clamping plate each have three slots at appropriate locations for receiving the locator pins to precisely position the panels and plates relative to each other.
Upon removal from the oven, the chip site defined by the openings in the stiffener panel is fluxed with a solder fluxing composition, at least one chip with a plurality of solder balls on its down side is placed in each cavity formed when one side of each stiffener opening was closed by the base panel, and the resulting C4 solder joints are then reflowed to bond each chip to the base panel. Each chip is then encapsulated in a polymeric material.
After curing of the encapsulating material, a cover panel is placed on the upper side of the stiffener panel with a silicone based adhesive therebetween. The cover panel also has three slots and is precisely located with the three locator pins. A second clamping plate is fastened to the resulting stacked structure to squeeze the adhesive to the correct dimension, and this clamped structure is placed in an oven to cure the adhesive. After removal from the oven, the second clamping plate and the carrier plate are removed, and the laminated composite panel is flipped over. A tacky flux and then solder balls are placed over exterior pads connected by conductive tracks to the interior terminal pads. The whole assembly is then further heated to reflow the solder balls so as to attach them to the exterior pads and form solder terminals on the exterior surface of the composite panel for connecting each chip to an electrical circuit for use therein.
The composite panel is then cut into individual chip modules each having one or more compartments, each of which houses one or more chips. As already described, the individual panels and plates each have three slots for receiving the three locator pins on the carrier plate. Similarly, the laminated composite panel has three corresponding slots for receiving three locator pins on a dicing saw table so as to precisely position the composite panel for cutting it into individual modules without breaching a chip compartment.